复旦大学  
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个人简介

学习工作经历:

研究方向:

科研项目:

代表性论文或专著:

  1. C. Ding#, Y. Huan#, H. Jia, Y. Yan, F. Yang, Z. Zou and L.R. Zheng,"An Ultra-Low Latency Multicast Router for Large-Scale Multi-Chip Neuromorphic Processing," 2021 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021. (Equal contribution)

  2. Y. Yan, H. Chu, X. Chen, Y. Jin, Y. Huan, L.R. Zheng and Z. Zou,"Graph-Based Spatio-Temporal Backpropagation for Training Spiking Neural Networks," 2021 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2021. (Equal contribution)

  3. J. Xu#, Y. Huan#, B. Huang, H. Chu, Y. Jin, L.R. Zheng, Z. Zou, “A Memory-Efficient CNN Accelerator Using Segmented Logarithmic Quantization and Multi-Cluster Architecture,” in IEEE Transactions on Circuits and Systems II: Express Briefs, 2020. (Equal contribution)

  4. J. Xu#, Y. Huan#, B. Huang, H. Chu, Y. Jin, L.R. Zheng, Z. Zou, “Base-Reconfigurable Segmented Logarithmic Quantization and Hardware Design for Deep Neural Networks,” in Journal of Signal Processing Systems, 2020. (Equal contribution)

  5. Y. Huan, N. Ma, J. Mao, S. Blixt, Z. Lu, Z. Zou and L. R. Zheng, "A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 63, no. 12, pp. 2245-2256, Dec. 2016. 

  6.  Y. Huan, N. Ma, S. Blixt, Z. Zou and L. Zheng, "A 61 μA/MHz reconfigurable application-specific processor and system-on-chip for Internet-of-Things," 2015 28th IEEE International System-on-Chip Conference (SOCC), Beijing, 2015, pp. 235-239. 

  7.  Y. Huan, Y. Qin, Y. You, L. Zheng and Z. Zou, "A multiplication reduction technique with near-zero approximation for embedded learning in IoT devices," 2016 29th IEEE International System-on-Chip Conference (SOCC), Seattle, WA, 2016, pp. 102-107. 

  8. Y. Huan, J. Xu, L. Zheng, H. Tenhunen and Z. Zou, "A 3D Tiled Low Power Accelerator for Convolutional Neural Network," IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.

  9. Y. Jin, Y. Huan, H. Chu, Z. Zou, L. Zheng, "TMR group coding method for optimized SEU and MBU tolerant memory design," IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018.

  10. J. Xu, Y. Huan, K. Yang, Y. Zhan, Z. Zhuo and L. Zheng, "Optimized Near-Zero Quantization Method for Flexible Memristor Based Neural Network," in IEEE Access, 2018.

  11. K. Yang, Y. Huan, J. Xu, Z. Zou, Y. Zhan, L. R. Zheng, F. Seoane, "Universal and Convenient Optimization Strategies for Three-Terminal Memristors," in IEEE Access, vol. 6, pp. 48815-48826, 2018.

  12. H. Chu, Y. Huan, D. Bao, B. Källbäck, Y. Qin, Z. Zou and L. R. Zheng, "An ASIC Design of Multi-Electrode Digital Basket Catheter Systems with Reconfigurable Compressed Sampling," 2018 31st IEEE International System-on-Chip Conference (SOCC), Arlington, VA, 2018, pp. 124-129.

  13.  I. Tcarenko, Y. Huan, D. Juhasz, A. M. Rahmani, Z. Zou, T. Westerlund, P. Liljeberg, L. Zheng and H. Tenhunen, "Smart energy efficient gateway for Internet of mobile things," 2017 14th IEEE Annual Consumer Communications & Networking Conference (CCNC), Las Vegas, NV, 2017, pp. 1016-1017.

  14.  Z. Zou, Y. Jin, P. Nevalainen, Y. Huan, J. Heikkonen and T. Westerlund, "Edge and Fog Computing Enabled AI for IoT-An Overview," 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hsinchu, Taiwan, 2019, pp. 51-56.

  15.  D. Bao, Z. Zou, Y. Huan, C. Zhai, T. Bagaian, H. Tenhunen, B. Källbäck, and L. Zheng. "A smart catheter system for minimally invasive brain monitoring." In 8th International Conference on Biomedical Electronics and Devices, BIODEVICES 2015; Lisbon; Portugal, 2015, pp. 198-203. 

  16.  L. Liu, J. Xu, Y. Huan, Z. Zou, S. Yeh and L. Zheng, "A Smart Dental Health-IoT Platform Based on Intelligent Hardware, Deep Learning and Mobile Terminal," in IEEE Journal of Biomedical and Health Informatics, 2019.

  17.  L. Liu, Y. Jin, Y. Liu, N. Ma, Y. Huan, Z. Zou, L. R. Zheng, "A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 10, pp. 2143-2154, Oct. 2018.

  18. N. Ma, Z. Zou, Z. Lu, Y. Huan and S. Blixt, L. Zheng,"A 101.4 GOPS/W reconfigurable and scalable control-centric embedded processor for domain-specific applications," 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, 2016, pp. 1746-1749. ns on Advanced Packaging, v 24, n 4, p 477-485, November 2016.

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  • 教育经历
  • 工作经历
  • 研究方向
  • 社会兼职
  • 2013.9
    2018.6
    复旦大学   → 微电子学与固体电子学   → 博士学位  → 博士研究生
  • 2009.9
    2013.6
    复旦大学   → 微电子学与固体电子学  → 大学本科
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