Academic Achievements
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization
Dec 16, 2021 |
  • Journal:
     PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC
  • Document Code:
     HS705
  • Page Number:
     146-151
  • Translation or Not:
     no
  • Date of Publication:
     Jan 1, 2021