严昌浩
( 教授
博士生导师
)
- 教师拼音名称：Yan Changhao
- 所在单位：集成电路与微纳电子创新学院
- 学历：研究生毕业
- 办公地点：上海浦东新区张衡路825号（复旦大学张江校区）微电子楼207
- 性别：男
- 学位：博士学位
- 在职信息：在职
- 主要任职：科研人员
- 朱恒亮；曾璇；崔涛；严昌浩；张林波,纳米集成电路互连线建模和光刻仿真中的大规模并行计算方法.-中国科学. 信息科学-2016-01-01-46
- 梁生欣；王梦硕；杨帆；严昌浩；曾璇；周电,基于物理设计约束的模拟电路尺寸设计的优化算法GMSGA.-复旦学报(自然科学版)-2019-01-01-58
- Lyu Wenlong；Yang Fan；Yan Changhao；Zhou Dian；Zeng Xuan,Multi-objective bayesian optimization for analog/RF circuit synthesis yangfan@fudan.edu.cn, xzeng@fudan.edu.cn.-2018 55TH ACM/ESDA/IEEE DESIGN AUTOMATION CONFERENCE (DAC)-2018-01-01-Part F137710
- Wei Xin；Yan Changhao；Zhou Hai；Zhou Dian；Zeng Xuan,An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel.-PROCEEDINGS OF THE 2019 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, DATE 2019-2019-01-01
- Yan, Changhao；Cai, Wei；Zeng, Xuan,A Highly Scalable Boundary Integral Equation and Walk-On-Spheres (BIE-WOS) Method for the Laplace Equation with Dirichlet Data.-Communications in Computational Physics-2021-01-01-29
- Shen, Yue；Yan, Changhao；Wang, Sheng-Guo；Zhou, Dian；Zeng, Xuan,An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays.-PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021)-2021-01-01-2021-February
- Zhang, Shuhan；Yang, Fan；Yan, Changhao；Zhou, Dian；Zeng, Xuan,An efficient batch constrained Bayesian optimization approach for analog circuit synthesis via multi-objective acquisition ensemble.-IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS-2022-01-01-41
- Wang Mengshuo；Yang Fan；Yan Changhao；Zeng Xuan；Hu Xiangdong,Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits.-PROCEEDINGS OF THE 2017 54TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC)-2017-01-01-Part 128280
- Cai, Junzhe；Yan, Changhao；Tao, Yudong；Lin, Yibo；Wang, Sheng-Guo；Pan, David Z.；Zeng, Xuan,A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method.-IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS-2021-01-01-40
- Huang, Jiangli；Yang, Fan；Yan, Changhao；Zhou, Dian；Zeng, Xuan,A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization.-PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC-2021-01-01
